VTT’s ferroelectric memory technology paves the way for hyper efficient AI computing

Contemporary memory solutions are all charge-based, and for high frequency computations with large data sets, such as AI computing, they are exceptionally ill-fitted: 

1. They are too slow and fail after only a few tens of thousands of reprogramming cycles (NAND-flash), 
2. They are volatile such that they lose their memory state within microseconds, making them extremely power hungry (DRAM), or
3. They have a large footprint, making them too expensive to integrate at scale (SRAM). 

Currently, AI computations almost exclusively rely on the power-hungry DRAM. As the energy consumption of AI continues to grow exponentially, the semiconductor industry is urgently seeking alternative memory solutions.

When performing computations for AI applications, beyond the limitations of the memory technology, there is also a large energy and performance penalty for moving huge amounts of data back and forth between the processor units and the memory cells. For a unified compute and memory cell, the memory needs to be non-volatile, meaning it does not require any energy to be maintained. Furthermore, the memory state needs to be measured in conductivity, not in stored charge that is depleted during the measurement.

It has been projected that the implementation of non-volatile ferroelectric hafnium-zirconium-oxide (HZO) based computational memory units can improve computational efficiency by several orders of magnitude, offering a much-needed path towards sustainable and cost-efficient AI. The results from the VTT developed technology platform represent important steps towards pilot-line fabrication, where the processing can be made much more invariant to overall process fluctuations, from centre-to-edge of a wafer.

VTT is developing a new type of low-power memory based on ultra-thin films of ferroelectric hafnium zirconium oxide (HZO). This material can retain its electrical polarisation even when power is switched off. The technology is highly energy efficient, fast to write and read, compact enough for integration in a small footprint, and capable of being reprogrammed more than a trillion times. When co-integrated with a selector, it can also enable analogue computing directly in memory. 

Simulations of different computational systems have shown that ferroelectric HZO memories could improve AI computational efficiency by more than 100 times compared with today’s leading alternatives, such as graphics processing units (GPUs). Importantly, once fully developed, HZO memories could reach the market relatively quickly as they can be manufactured using processes already familiar to the semiconductor industry.

In this work, 5.5-nm-thick ferroelectric HZO metal-insulator-metal (MIM) capacitors with different sublayer thicknesses were characterized to investigate the impact on wafer scale performance distributions. The study includes standard solid solution HZO (SS-HZO, alternated every 1 atomic layer) and superlattice HZO (SL-HZO, alternated every 5 atomic layers). It has been shown in the literature prior that the ferroelectric performance of individual devices can be improved by implementing SL-HZO. VTT’s findings take this one step further, that by implementing SL-HZO, the co-variance to process fluctuations, such as the underlying metal film thickness, across a wafer is significantly reduced, with robust switching behaviour from the centre to the edge, showcasing state-of-the-art performance.

The samples were made in the OtaNano cleanroom in Micronova in Espoo as part of VTT’s work to develop a non-volatile memory pilot line within the EU Chips Act and Business Finland funded FAMES project. A pilot line is a bridge between laboratory research and industrial manufacturing by proving that a technology can be produced in a controlled, repeatable and scalable way.

To support this work, VTT has also strengthened its measurement capabilities with new equipment acquired through the FAMES project. These tools help researchers check device performance more accurately and monitor manufacturing quality more closely. The demonstrated wafer-scale uniformity is therefore not only a scientific result, but also a sign of progress toward a reliable technology platform for future energy-efficient memory solutions.

The next steps include co-integration with a back-end-of-line selector device, substantial footprint scaling, as well as continued improvement of yield and process repeatability. A future VTT non-volatile memory platform could be implemented in compute-in-memory solutions but also offer customers a high degree of flexibility for innovative explorations.

The research project funded by EU Chips JU and Business Finland started in December 2023 and will run until December 2028. The total budget of the consortium is approximately EUR 830 million, of which VTT’s share is approximately EUR 32 million.